R5F51406ADFN datasheet(97/121 Pages) RENESAS

97 / 121 page

R01DS0379EJ0120 Rev.1.20

Page 97 of 121

Nov 22, 2024

RX140 Group

2. Electrical Characteristics

2.10

CTSU Characteristics

2.11

Power-On Reset Circuit and Voltage Detection Circuit Characteristics

Note:

These characteristics apply when noise is not superimposed on the power supply. When a setting is made so that the voltage

detection level overlaps with that of the voltage detection circuit (LVD2), it cannot be specified which of LVD1 and LVD2 is used

for voltage detection.

Table 2.69

CTSU Characteristics

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

External capacitance connected to TSCAP pin

Ctscap

910

Permissible output

high/low current

P12 to P17, P20, P21, P26, P27,

P30 to P32, P34, P35, P54, P55,

PB1 to PB7, PC2 to PC7,

PH0 to PH3

| ΣIOH |

+ ΣIOL

—

When VXSEL = 0

PA0, PA1, PA3, PA4, PA6, PB0,

PE0 to PE5

—

[Products with 64

Kbytes of flash

memory or less]

When VXSEL = 0

PA0 to PA6, PB0, PD0 to PD2,

PE0 to PE5

—

[Products with at

least 128 Kbytes

of flash memory]

When VXSEL = 0

Table 2.70

Power-On Reset Circuit and Voltage Detection Circuit Characteristics (1)

Conditions: 1.8 V ≤ VCC ≤ 5.5 V, 1.8 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, Ta = –40 to +105°C

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Voltage detection

level

Power-on reset (POR)

VPOR

1.35

1.50

1.65

Figure 2.58, Figure 2.59

Voltage detection circuit

(LVD0)*1

Vdet0_0

3.67

3.85

3.97

Figure 2.60

At falling edge VCC

Vdet0_1

2.70

2.85

3.00

Vdet0_2

2.37

2.53

2.67

Vdet0_3

1.80

1.90

1.99

Voltage detection circuit

(LVD1)*2

Vdet1_0

4.12

4.29

4.42

Figure 2.61

At falling edge VCC

Vdet1_1

3.98

4.16

4.28

Vdet1_2

3.86

4.03

4.16

Vdet1_3

3.68

3.86

3.98

Vdet1_4

2.99

3.10

3.29

Vdet1_5

2.89

3.00

3.19

Vdet1_6

2.79

2.90

3.09

Vdet1_7

2.68

2.80

2.98

Vdet1_8

2.57

2.68

2.87

Vdet1_9

2.47

2.59

2.67

Vdet1_A

2.37

2.48

2.57

Vdet1_B

2.10

2.20

2.30

Vdet1_C

1.86

1.96

2.06

Vdet1_D

1.80

1.86

1.96

Voltage detection

level

Voltage detection circuit

(LVD2)*3

Vdet2_0*4

4.08

4.32

4.48

Figure 2.62

At falling edge VCC

Vdet2_1

3.95

4.17

4.35

Vdet2_2

3.82

4.03

4.22

Vdet2_3

3.62

3.84

4.02

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