R5F526TBCDFM datasheet(89/142 Pages) RENESAS

89 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 89 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5.9

SCI

Note 1. tPBcyc: PCLKB cycle

Figure 2.36

SCK Clock Input Timing

Figure 2.37

SCI Input/Output Timing: Clock Synchronous Mode

Table 2.31

SCIk and SCIh Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test Conditions

SCIk, SCIh Input clock cycle

Asynchronous

tScyc

—

tPBcyc Figure 2.36

Clock synchronous

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—5

Input clock fall time

tSCKf

—5

Output clock cycle

Asynchronous (SCIk)

tScyc

6—

tPBcyc

Asynchronous (SCIh)

—

Clock synchronous

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—5

Output clock fall time

tSCKf

—5

Transmit data delay time

Clock synchronous

tTXD

—28

VCC ≥ 4.5 V

Figure

2.37

—

VCC < 4.5 V

Receive data setup time

Clock synchronous

tRXS

—

Figure 2.37

Receive data hold time

Clock synchronous

tRXH

5—

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 1, 5, 6, and 12)

tTXD

tRXS tRXH

TxDn

RxDn

SCKn

n = 1, 5, 6, and 12

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