R5F526TBCDFM datasheet(8/142 Pages) RENESAS

8 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 8 of 142

Oct 31, 2024

RX26T Group

1. Overview

Communication

function

I3C bus interface (RI3C)

 1 channel

Supports the SDR mode

Supports the legacy I2C message

Supports the multi-master

 Event linking by the ELC

CAN FD module

(CANFD)

 1 channel

 Compliance with the ISO11898-1:2015 specification (standard frame and extended

frame)

Serial peripheral

interface (RSPId)

 1 channel

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

Transmit/receive data can be swapped in byte units

 Buffered structure

Double buffers for both transmission and reception

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

Serial peripheral

interface (RSPIA)

 1 channel

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

Transmit/receive data can be swapped in byte units

 Buffered structure

The transmission and reception sections have 4-stage and 32-bit-wide FIFO buffers for

the sequential transmission and reception of data.

 RSPCK can be stopped with the receive buffer full for master reception.

 Event linking by the ELC

 Communications protocol: RSPIA supports the Texas Instruments Synchronous Serial

Protocol (TI SSP).

Table 1.1

Outline of Specifications (7/9)

Classification

Module/Function

Description

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