R7KA8M2AFDCAC datasheet(175/295 Pages) RENESAS

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Table 2.64

OSPI timing (3 of 9)

Conditions:

High-speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_SCLK,

OM_n_SCLKN, OM_n_SIO7-0, OM_n_DQS.

Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_CS0, OM_n_CS1.

Load capacitance C = 15pF

Item

Symbol

VCC/VCC2 VDD

Min

Max

Unit

Note

Data input/output slew rate

tSR

2.70 V or

above

VSCR_1,

voltage

range 1

1.72

—

Figure 2.83

VSCR_2,

voltage

range 2

1.37

—

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

0.75

—

VSCR_2,

voltage

range 2

Data input setup

time (to

OM_SCLK/

OM_SCLKN)

SDR without

OM_DQS

tSU

2.70 V or

above

VSCR_1,

voltage

range 1

8.17

—

Figure 2.84

VSCR_2,

voltage

range 2

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

13.0

—

VSCR_2,

voltage

range 2

Data input hold

time (to

OM_SCLK/

OM_SCLKN)

2.70 V or

above

VSCR_1,

voltage

range 1

0.5

—

VSCR_2,

voltage

range 2

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

0.5

—

VSCR_2,

voltage

range 2

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 175 of 295

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