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R7KA8M2AFDCAM bảng dữ liệu(PDF) 168 Page - Renesas Technology Corp

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Table 2.63
SPI timing (5 of 5)
Conditions:
1. High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:
RSPCLKA_B, RSPCLKB_B.
For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
2. Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership.
3. Load capacitance C = 15pF is applied to the VCC/VCC2 condition “3.00 V or above”.
Parameter
High Speed/
Default
VCC/VCC2
Symbol
Min
Max
Unit
Note
Successive
transmission
delay time
Master
—
3.00 V or above
tTD
tSPcyc + 2 × tTcyc
8 × tSPcyc
+ 2 × tTcyc
ns
Figure 2.76,
Figure 2.77
—
2.70 V or above
tSPcyc + 2 × tTcyc
8 × tSPcyc
+ 2 × tTcyc
—
1.62 V or above
tSPcyc + 2 × tTcyc
8 × tSPcyc
+ 2 × tTcyc
Slave
—
3.00 V or above
tTcyc
—
ns
—
2.70 V or above
tTcyc
—
—
1.62 V or above
tTcyc
—
MOSI and
MISO rise
and fall time
Output
—
3.00 V or above
tDr, tDf
—
1.66
ns
—
2.70 V or above
—
3.30
—
1.62V or above
—
6.60
Input
—
3.00 V or above
—
1.0
μs
—
2.70 V or above
—
1.0
—
1.62 V or above
—
1.0
SSL rise and
fall time
Output
—
3.00- V or above tSSLr,
tSSLf
—
1.66
ns
—
2.70 V or above
—
3.30
—
1.62 V or above
—
6.60
Input
—
3.00 V or above
—
1.0
μs
—
2.70 V or above
—
1.0
—
1.62 V or above
—
1.0
Slave access
time
Slave
—
3.00 V or above
tSA
—
20.0
ns
Figure 2.79,
Figure 2.80
—
2.70 V or above
—
20.0
—
1.62 V or above
—
25.0
Slave output
release time
Slave
—
3.00 V or above
tREL
—
20.0
ns
—
2.70 V or above
—
20.0
—
1.62 V or above
—
25.0
Note:
tTcyc: TCLK cycle.
Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, to indicate group membership. SPI0 and SPI1 are
instance _B.
Note 2. All pins of group membership can be used.
Note 3. 1 µs at the longest
RA8M2 Datasheet
2. Electrical Characteristics
R01DS0438EJ0130 Rev.1.30
Feb 27, 2026
Page 168 of 295



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