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Table 2.63
SPI timing (4 of 5)
Conditions:
1. High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:
RSPCLKA_B, RSPCLKB_B.
For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.
2. Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership.
3. Load capacitance C = 15pF is applied to the VCC/VCC2 condition “3.00 V or above”.
Parameter
High Speed/
Default
VCC/VCC2
Symbol
Min
Max
Unit
Note
TI SSP SS
input setup
time
Slave
—
3.00 V or above
tTISS
2.5
—
ns
Figure 2.81
—
2.70 V or above
2.5
—
—
1.62 V or above
2.5
—
TI SSP SS
input hold
time
Slave
—
3.00 V or above
tTISH
2.5
—
ns
—
2.70 V or above
2.5
—
—
1.62 V or above
5.5
—
TI SSP next-
access time
Slave
—
3.00 V or above
tTIND
2 × tTcyc + SLNDL × tTcyc
—
ns
—
2.70 V or above
2 × tTcyc + SLNDL × tTcyc
—
—
1.62 V or above
2 × tTcyc + SLNDL × tTcyc
—
TI SSP
master SS
output delay
Master
—
3.00 V or above
tTISSOD
—
4.0
ns
Figure 2.78
—
2.70 V or above
—
8.0
—
1.62 V or above
—
8.0
Data output
delay time
Master
—
3.00 V or above
tOD1
—
2.0
ns
Figure 2.76,
Figure 2.77
—
2.70 V or above
—
3.0
—
1.62 V or above
—
6.0
High Speed*1 3.00 V or above
tOD2
—
1.5
High Speed*1 2.70 V or above
—
2.5
High Speed*1 1.62 V or above
—
4.5
Default*2
3.00 V or above
—
2.5
Default*2
2.70 V or above
—
2.5
Default*2
1.62 V or above
—
4.5
Slave
—
3.00 V or above
tOD
—
10.0
—
2.70 V or above
—
13.5
—
1.62 V or above
—
21.5
Data output
hold time
Master
High Speed*1 3.00 V or above
tOH
−1.5
—
ns
High Speed*1 2.70 V or above
−2.5
—
High Speed*1 1.62 V or above
−4.5
—
Default*2
3.00 V or above
−2.5
—
Default*2
2.70 V or above
−2.5
—
Default*2
1.62 V or above
−4.5
—
Slave
—
3.00 V or above
0.0
—
—
2.70 V or above
0.0
—
—
1.62 V or above
0.0
—
RA8M2 Datasheet
2. Electrical Characteristics
R01DS0438EJ0130 Rev.1.30
Feb 27, 2026
Page 167 of 295



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