R7KA8M2ADECAC datasheet(157/295 Pages) RENESAS

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Table 2.60

SCI timing (Simple SPI) (2 of 3)

Condition 1: VCC/VCC2 = 2.70 V or above

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Condition 2: VCC/VCC2 = 1.62 V or above

Following pins have high-speed high-drive output selected in the Port Drive Capability bit in the PmnPFS register: SCK1_A, SCK1_C,

SCK3_A, SCK4_A, SCK4_B, SCK4_C and SCK6_B

Other pins have high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC=VCC2.

Parameter

High

Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

Data input setup

time

Master

High

Speed*1

2.70 V or above

tSU

-1.5

—

Figure 2.70,

Figure 2.71

1.62 V or above

-1.5

—

Default*2

2.70 V or above

2.0

—

1.62 V or above

2.0

—

Slave

Default*2

2.70 V or above

2.5

—

1.62 V or above

4.5

—

Data input hold

time

Master

High

Speed*1

2.70 V or above

7.5

—

1.62 V or above

9.5

—

Default*2

2.70 V or above

7.5

—

1.62 V or above

9.5

—

Slave

Default*2

2.70 V or above

2.5

—

1.62 V or above

4.5

—

Data output delay

Master

High

Speed*1

2.70 V or above

tOD

—

3.0

1.62 V or above

—

4.5

Default*2

2.70 V or above

—

3.5

1.62V or above

—

5.5

Slave

High

Speed*1

2.70 V or above

—

12.5

1.62 V or above

—

20.5

Default*2

2.70 V or above

—

18.5

1.62 V or above

—

26.5

Data output hold

time

Master

High

Speed*1

2.70 V or above

tOH

−3.0

—

1.62 V or above

−4.5

—

Default*2

2.70 V or above

−3.5

—

1.62 V or above

−5.5

—

Slave

Default*2

2.70 V or above

0.0

—

1.62 V or above

0.0

—

Data rise and fall

time

Output

—

2.70 V or above

tDr, tDf

—

3.3

1.62 V or above

—

6.6

Input

—

2.70 V or above

—

1.62 V or above

—

SS input setup time

—

1.62 V or above

tLEAD

1.0

—

tSPcyc Figure 2.72,

Figure 2.73

SS input hold time

—

1.62 V or above

tLAG

1.0

—

tSPcyc

SS input rise and fall time

—

1.62 V or above

tSSLr, tSSLf

—

µs

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 157 of 295

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