R7FA6T2AB3CNE datasheet(24/101 Pages) RENESAS

24 / 101 page

2.2.5

Operating and Standby Current

Table 2.7

Operating and standby current

Parameter

Symbol Min Typ Max Unit Test conditions

Supply

current*1

High-speed

mode

Maximum*2

ICC*3

—

150 mA

ICLK = 240 MHz

PCLKA = 120 MHz

PCLKB = 60 MHz

PCLKC = 60 MHz

PCLKD = 120 MHz

FCLK = 60 MHz

CoreMark®*5 *6

—

Normal mode

All peripheral clocks enabled,

while (1) code executing from

flash*4

—

All peripheral clocks disabled,

while (1) code executing from

flash*5 *6

—

Sleep mode*5 *6

—

Increase

during BGO

operation

Data flash P/E

—

Code flash P/E

—

Low-speed mode*5 *10

—

ICLK = 1 MHz

Software Standby mode

SNZCR.RXDREQEN = 1

—

ICLK = 32.768 kHz

SNZCR.RXDREQEN = 0

—

5.1

—

Deep

Software

Standby mode

Power supplied to Standby SRAM

—

22.7 60

µA

—

Power not

supplied to

SRAM

Power-on reset circuit low power

function disabled

—

11.3 30

—

Power-on reset circuit low power

function enabled

—

4.4

—

Inrush current on returning from deep

software standby mode

Inrush current*7

IRUSH

—

160 —

—

Energy of inrush

current*7

ERUSH

—

1.0

—

µC

—

Analog power

supply current

During A/D conversion (1unit)

Without SH

AICC

—

4.9

6.0

—

With SH

—

8.4

11.5 mA

—

PGA (1channel)

—

ACMPHS (1unit)

—

0.1

0.2

—

Temperature sensor

—

0.1

0.2

—

During D/A conversion (1channel)*8

Without AMP output

—

0.2

0.3

—

With AMP output

—

0.8

1.3

—

Waiting for A/D, D/A conversion (all units)

—

3.8

4.5

—

ADC, DAC12 in standby modes (all units)*9

—

0.7

µA

—

Reference

power supply

current

(VREFH0)

During A/D conversion (1unit)

SAR mode

AIREFH0 —

µA

—

Oversampling mode

and Hybrid mode

—

100 160 µA

—

Waiting for A/D conversion (all units)

—

µA

—

ADC in standby modes (all units)*9

—

0.03 1

µA

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.

Note 3. ICC depends on f (ICLK) as follows.

ICC Max. = 0.34 × f + 67 (max. operation in high-speed mode)

ICC Typ. = 0.095 × f + 4.7 (normal operation in high-speed mode, all peripheral clocks disabled)

ICC Typ. = 0.9 × f + 4.1 (low-speed mode)

ICC Max. = 0.045 × f + 67 (sleep mode)

Note 4. This does not include the BGO operation.

Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.75 MHz).

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

Page 24 of 101

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