R7FA6T2AB3CNE datasheet(4/101 Pages) RENESAS

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Table 1.6

Timers (2 of 2)

Feature

Functional description

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt or an underflow interrupt. Because the timer

operates with an independent, dedicated clock source, it is particularly useful in returning the

MCU to a known state as a fail-safe mechanism when the system runs out of control. The IWDT

can be triggered automatically by a reset, underflow, refresh error, or a refresh of the count value

in the registers.

Table 1.7

Communication interfaces

Feature

Functional description

Serial Communications Interface (SCI)

The Serial Communications Interface (SCI) × 6 channels have asynchronous and synchronous

serial interfaces:

● Asynchronous interfaces (UART and Asynchronous Communications Interface Adapter

(ACIA))

● 8-bit clock synchronous interface

● Simple IIC (master-only)

● Simple SPI

● Simple LIN

● Smart card interface

● Manchester interface

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol. SCIn (n = 0 to 4, 9) has FIFO buffers to enable continuous and full-duplex

communication, and the data transfer speed can be configured independently using an on-chip

baud rate generator.

I2C bus interface (IIC)

The I2C bus interface (IIC) has 2 channels. The IIC module conform with and provide a subset of

the NXP I2C (Inter-Integrated Circuit) bus interface functions.

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) has 2 channels. The SPI provides high-speed full-duplex

synchronous serial communications with multiple processors and peripheral devices.

CAN with Flexible Data-rate (CANFD)

The CAN with Flexible Data-rate (CANFD) module can handle classical CAN frames and CAN-

FD frames complied with ISO 11898-1 standard.

The module supports 4 transmit buffers and 32 receive buffer.

Table 1.8

Analog

Feature

Functional description

A/D Converter (ADC)

The A/D Converter (ADC) has two units of noise-shaping SAR-type A/D converter.

● Hybrid architecture that combines the features of the successive approximation register-

type and the delta-sigma modulation-type.

● Up to 16-bit resolution

● Up to 6.25 Msps

● Up to 29 analog input channels

● Support single-ended input or differential inputs

● Built-in channel-dedicated sample-and-hold circuit (SH)

● Built-in Programmable Gain Amplifier (PGA)

● Temperature sensor output and internal reference voltage, and D/A converters output are

selectable for conversion.

12-bit D/A Converter (DAC12)

A 12-bit D/A converter (DAC12) is provided.

High-Speed Analog Comparator

(ACMPHS)

The High-Speed Analog Comparator (ACMPHS) compares a test voltage with a reference

voltage and provides a digital output based on the conversion result. Both the test and reference

voltages can be provided to the comparator from internal sources such as the DAC12 output

and an internal PGA output, and an external source. Such flexibility is useful in applications

that require go/no-go comparisons to be performed between analog signals without necessarily

requiring A/D conversion.

Temperature Sensor (TSN)

The on-chip Temperature Sensor (TSN) determines and monitors the die temperature for

reliable operation of the device. The sensor outputs a voltage directly proportional to the die

temperature, and the relationship between the die temperature and the output voltage is fairly

linear. The output voltage is provided to the ADC for conversion and can be further used by the

end application.

RA6T2 Datasheet

1. Overview

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

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