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R7FA6T2AB3CNB bảng dữ liệu(PDF) 45 Page - Renesas Technology Corp |
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R7FA6T2AB3CNB bảng dữ liệu(HTML) 45 Page - Renesas Technology Corp |
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45 / 101 page ![]() tSCKW tSCKr tSCKf tScyc SCKn Note: n = 0 to 4, 9 Figure 2.32 SCK clock input/output timing Table 2.24 SCI timing (Simple SPI) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter High Speed/ Default Symbol Min Max Unit Note SCK clock cycle output Master tSPcyc 2 65536 tTcyc SCK clock cycle input Slave 2 — SCK clock high pulse width Master tSPCKWH 0.4 0.6 tSPcyc Slave SCK clock low pulse width Master tSPCKWL 0.4 0.6 tSPcyc Slave SCK clock rise and fall time Output tSPCKr, tSPCKf — 5 ns Input — 1 us Data input setup time Master High Speed*1 tSU 1.7 — ns Default*2 3 — ns Slave 3.3 — ns Data input hold time Master High Speed*1 tH 12 — ns Default*2 14 — ns Slave 3 — ns Data output delay Master High Speed*1 tOD — 5 ns Default*2 — 7.3 ns Slave High Speed*1 — 15 ns Default*2 — 21 ns Data output hold time Master tOH 0 — ns Slave 0 — ns Data rise and fall time Output tDr, tDf — 5 ns Input — 1 ns Slave access time tSA — 5 tTcyc Slave output release time tREL — 5 tTcyc Note: tTcyc: SCITCLK cycle. Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SCI0 is instance _A, SCI2 and SCI3 are instance _B, SCI1 and SCI9 are instance _C, SCI4 is instance _C and RXD is only PD14. Note 2. All pins of group membership can be used. Table 2.25 SCI timing (Simple SPI mode) (1 of 2) Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register. Parameter Symbol Min Max Unit Note SS input setup time tLEAD 1 — tSPcyc RA6T2 Datasheet 2. Electrical Characteristics R01DS0400EJ0150 Rev.1.50 Jul 2, 2025 Page 45 of 101 |
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