AS3953A-BDFM datasheet(47/71 Pages) AMSOSRAM

47 / 71 page

Page 46

ams Datasheet

Document Feedback

[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Set Default

This direct command puts the AS3953A in the same state as

power-up initialization. All registers are initialized to the default

state.

Clear

This direct command stops all current activities (transmission

or reception) and clears FIFO.

Transmit

This direct command transmits the data stored in the FIFO. In

Protocol modes it is only accepted on Level-4 of

communication. Before triggering transmission using Transmit

command direct command Clear has to be sent, followed by

definition of number of transmitted bytes and writing data to

be transmitted in FIFO.

Execution of this direct command is only enabled when the

AS3953A antenna coil is in a PCD field (VP_INT is above HF_PON

threshold).

Go2halt

Puts PICC logic in HALT state.

Execution of this direct command is only enabled when the

AS3953A antenna coil is in a PCD field (VP_INT is above HF_PON

threshold) and PICC Logic is in one of the two ISO 14443A

Protocol modes.

Registers

The 6-bit register addresses below are defined in the

hexadecimal notation. The possible address range is from 00h

to 3Fh.

There are two types of registers implemented in the AS3953A:

configuration registers and display registers. The configuration

registers are used to configure the AS3953A. They can be

written and read through the SPI (RW). The display registers are

read only (RO); they contain information about the AS3953A

internal state, which can be accessed through the SPI.

AS3953A-BDFM bảng dữ liệu(PDF) 47 Page - ams-OSRAM AG