AS3953A-BDFM datasheet(36/71 Pages) AMSOSRAM

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ams Datasheet

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[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

Writing of Data to Addressable Registers (Register

Write Mode)

Following figures show cases of writing a single byte and

writing multiple bytes with auto-incrementing address. After

the SPI operation mode bits, the address of register to be

written is provided. Then one or more data bytes are transferred

from the SPI, always from the MSB to the LSB. The data byte is

written in register on falling edge of its last clock. In case the

communication is terminated by putting /SS high before a

packet of 8 bits composing one byte is sent, writing of this

address does not exist or it is a read only register no write is

performed.

Note(s): When the AS3953A is powered via vp_SPI and not via

field; the registers and EEPROM can be readout. When CS is set

to low, after 50us of the falling edge, the Registers and the

EEPROM can be readout. Nevertheless, if there is no activity for

1ms, there is a timeout and the logic goes to sleep, hence losing

the values in the registers. (EEPROM values are retained).

Figure 42:

Writing of a Single Register

Figure 43:

Writing of Register Data with Auto-Incrementing Address

SCLK rising

edge Data is

transfered from

µC

SCLK falling

edge Data is

sampled

Data is moved to

Address

A4-A0

/SS rising

edge signals

end of WRITE

Mode

Three leading

bits indicate

Mode

/SS

SCLK

MOSI

000

Data is moved to

Address

<A4-A0> + n

/SS raising edge

signals end of

WRITE Mode

Three leading

bits indicate

Mode

Data is moved to

Address

<A4-A0> + (n-1)

Data is moved to

Address

<A4-A0> + 1

Data is moved

to Address

<A4-A0>

/SS

SCLK

MOSI

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