EM78F651NAPSSLASHNAPJ datasheet(26/58 Pages) EMC

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EM78F651N

8-Bit Microcontroller

•

Product Specification (V1.1) 10.20.2006

(This specification is subject to change without further notice)

When power is switched on, the upper three bits of R3 are cleared.

The bits of the RB, RC, RD, RD, RE registers are set to their previous status.

The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).

The bits of the IOCA register are set to all "1".

The bits of the IOCB register are set to all "1".

The IOCC register is cleared.

The bits of the IOCD register are set to all "1".

Bit 7 of the IOCE register is set to "1", and Bits 4 and 6 are cleared.

Bits 0~2 of RF and Bits 0~2 of IOCF register are cleared.

Sleep (power down) mode is asserted by executing the “SLEP” instruction. While

entering sleep mode, WDT (if enabled) is cleared but keeps on running. After a wake-

up, in RC mode the wake-up time is 34 clocks, High crystal mode wake-up time is 2 ms

and 32 clocks. In low crystal mode, wake-up time is 500 ms. The controller can be

awakened by:

(1) External reset input on /RESET pin

(2) WDT time-out (if enabled), or

(3) Port 6 input status changes (if enabled)

The first two cases will cause the EM78F651N to reset. The T and P flags of R3 can

be used to determine the source of the reset (wake-up). The third case must set RA

bit6, the 1 bit decide what’s wake-up source to wake-up EM78F651N. Before SLEP

instruction, enable the IOCF.1, the third case is considered the continuation of

program execution and the global interrupt ("ENI" or "DISI" being executed) decides

whether or not the controller branches to the interrupt vector following wake-up. If

ENI is executed before SLEP, the instruction will begin to execute from the address

006H after wake-up. If DISI is executed before SLEP, the operation will restart from

the succeeding instruction right next to SLEP after wake-up. In IOCF.1 disable

before SLEP instruction, after wake-up EM78F651N will restart and execute next

instruction sequentially.

In Case 2, can be enabled before entering the sleep mode and Case 3, must be

disabled. That is,

[a] if Port 6 Input Status Change Interrupt and External interrupt(/INT) are enabled

before SLEP, WDT must be disabled by software. However, the WDT bit in the

option register remains enabled. Hence, the EM78F651N, can be awakened only

by Case 1 or 3.

EM78F651NAPS/NAPJ bảng dữ liệu(PDF) 26 Page - ELAN Microelectronics Corp