4

PS8934A

01/21/08

PI2EQX5864

5.0Gbps 4-Lane PCI Express GenII Re-Driver

Output Configuration

The PI2EQX5864 provides flexible output strength and emphasis controls to provide the optimum signal to pre-compensate for

losses across long trace or noisy environments so that the receiver gets a clean with good eye opening. Control of output configura-

tion is grouped for the A and B channels, so that each channel within the group has the same setting.

settings for output level control, as specified by the SELx_y registers.

Output Swing Control

S1_[A:B]

S0_[A:B]

Swing (Diff. VPP)

001V

0

1

0.5V

1

0

0.7V

1

1

0.9V

Output De-emphasis Adjustment

D2_[A:B]

D1_[A:B]

D0_[A:B]

De-emphasis

0000dB

0

0

1

-2.5dB

0

1

0

-3.5dB

0

1

1

-4.5dB

1

0

0

-5.5dB

1

0

1

-6.5dB

1

1

0

-7.5dB

1

1

1

-8.5dB

Emphasis settings are determined by the state of the Dx_y input pins and configuration registers, as shown below. De-Emphasis is

selected as the default power-on mode in following the PCI Express specification, but can be changed to Pre-emphasis via repro-

gramming the Loopback and Emphasis Control register using the I2C interface.

Card Present Function

The PRSNT2# input allows direct control of the number of active lanes using the PRSNT2# signal from a PCI Express connector or

cable. PRSNT2# is a level sensitive input pin, and controls both directions of the receiver detect function. The receiver detect state

machine is only active when PRSNT2# is low, otherwise, the input termination will be high-impedance and output termination will

be 2K-Ohm. See the I/O operation table for more information.

Input Level Detect

An input level detect and output squelch function is provided on each channel to eliminate re-transmission of input noise. A continu-

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