M41T93 datasheet(28/51 Pages) STMICROELECTRONICS

tên linh kiện	M41T93

Giải thích chi tiết về linh kiện	Serial SPI bus RTC with battery switchover

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Clock operation

M41T93

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3.6

Optional second programmable alarm

When the Alarm 2 Enable (AL2E) Bit (D1 of address 13h) is set to a logic ‘1,’ registers 14h

through 18h provide control for a second programmable alarm which operates in the same

manner as the alarm function described above.

The AL2E Bit defaults on initial power-up to a logic ‘0’ (Alarm 2 disabled). In this mode, the

five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of

user SRAM.

Figure 14.

Alarm interrupt reset waveform

Figure 15.

Back-up mode alarm waveform

Note:

ABE and A1IE Bits = 1.

ALARM FLAG BITS (AFx)

0Fh

0Eh

00h

HIGH-Z

AI11823

IRQ/FT/OUT

VCC

IRQ/FT/OUT

AFx Bits in Flags

HIGH-Z

VSO

VPFD

trec

AI11824

Table 6.

Alarm repeat modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm setting

11111

Once per Second

11110

Once per Minute

11100

Once per Hour

11000

Once per Day

10000

Once per Month

00000

Once per Year

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