 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ICS9LPR426A bảng dữ liệu(PDF) 13 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS9LPR426A bảng dữ liệu(HTML) 13 Page - Integrated Circuit Systems |
|
|
13 / 21 page  13 Integrated Circuit Systems, Inc. ICS9LPR426A Advance Information 1346—10/23/07 I2C Table: PCIEX PLL Frequency Control Register Byte 15 Name Control Function Type PWD Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X I2C Table: PCIEX PLL Frequency Control Register: Byte 16 Name Control Function Type PWD Bit 7 N Div10 RW X Bit 6 N Div9 RW X Bit 5 N Div8 RW X Bit 4 N Div7 RW X Bit 3 N Div6 RW X Bit 2 N Div5 RW X Bit 1 N Div4 RW X Bit 0 N Div3 RW X Bytes 17,18 are reserved I2C Table: PCIEX PLL Frequency Select Select Register Byte 19 Name Control Function Type PWD Bit 7 Reserved Reserved RW 0 Bit 6 Reserved Reserved RW 0 Bit 5 Reserved Reserved RW 0 Bit 4 FS4 Freq Select Bit 4 RW 0 Bit 3 FS3 Freq Select Bit 3 RW 0 Bit 2 FSLC Freq Select Bit 2 RW Latch Bit 1 FSLB Freq Select Bit 1 RW Latch Bit 0 FSLA Freq Select Bit 0 RW Latch I2C Table: Output Control Register Byte 20 Name Control Function Type PWD Bit 7 48Mhz Strength Control RW 0 Bit 6 CPU_1 Free running Control RW 0 Bit 5 Load Control IIC Load control RW 0 Bit 4 CPUCLK_2/ITP Free-Running Controls RW 0 Bit 3 Reserved Reserved RW 1 Bit 2 Reserved Reserved RW 1 Bit 1 CPUCLK_0 Free Running Controls RW 0 Bit 0 RESET Sync Reset Synchronization upon Reset (Byte 21) RW 0 I2C Table: Synchronization Control Register Byte 21 Name Control Function Type PWD Bit 7 Reserved Reserved RW 1 Bit 6 Reserved Reserved RW 1 Bit 5 Reserved Reserved RW 1 Bit 4 Reserved Reserved RW 1 Bit 3 Reserved Reserved RW 1 Bit 2 Reserved Reserved RW 1 Bit 1 Reserved Reserved RW 1 Bit 0 Reserved Reserved RW 1 0 N Divider Programming Byte16 bit(7:0) and Byte15 bit(7:6) The decimal representation of M and N Divider in Byte 15 and 16 will configure the PCI PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 24 x Ndiv(10:0)/Mdiv(5:0) The decimal representation of M and N Divider in Byte 15 and 16 will configure the PCI PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 24 x Ndiv(10:0)/Mdiv(5:0) - M Divider Programming bit (5:0) - 0 Load - Stoppable Stoppable Do not Load 1 - - - Stoppable - - - - - - 0 01 - - - 1 Free-Running 01 1x 2x -- 1 Disable Enable - - - - - See Table 2: PCIEX PLL Frequency Selection Table Free-Running - Free-Running - -- |
|
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
