AM6421 datasheet(80/273 Pages) TI2

80 / 273 page

Table 5-58. Power Supply Signal Descriptions (continued)

SIGNAL NAME [1]

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

VSS

GND

Ground

A1, A21, A5, A6,

AA1, AA15,

AA18, AA21,

C10, C15, C3,

D1, E11, E13,

F10, F15, F8,

G1, G16, G3,

G7, G9, H11,

H20, H21, H6,

H8, J14, J7, J9,

K6, K8, L1, L16,

L3, L7, L9, M10,

M12, M6, M8,

N11, N13, N15,

N7, N9, P1, P10,

P18, P6, P8,

R12, R7, R9,

T10, T11, T15,

T16, T8, U3,

V17, W10, W18,

Y14, Y17, Y19

(1)

This pin must always be connected via a 6.3V or greater, 0.8uF to 1.5μF capacitor to VSS if the respective VDDSHVx pin is ever

operated at 3.3V. The capacitor selected must provide a capacitance within the defined range after it has been derated for DC-bias,

operating temperature, and aging effects. There are three connection options if the respective VDDSHVx pin is only operated at 1.8V.

The pin can be connected to the same decoupling capacitor that is required for 3.3V operation, it can be left unconnected, or it can be

connected to the same 1.8V power source as the respective VDDSHVx pin.

(2)

This pin must always be connected via a 6.3V or greater, 3.3μF ±20% capacitor to VSS when the SDIO_LDO is being used to

source VDDSHV5. The capacitor selected must provide a capacitance within the defined range after it has been derated for DC-bias,

operating temperature, and aging effects. Otherwise, this pin may be connected directly to VSS when the VDDA_3P3_SDIO pin is also

connected directly to VSS.

5.3.19 PRU_ICSSG

Note

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU

GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in

the device TRM.

5.3.19.1 MAIN Domain

Table 5-59. PRU_ICSSG0 Signal Descriptions

SIGNAL NAME [1]

SIGNAL

TYPE [2]

DESCRIPTION [3]

ALV/ANI PIN [4]

PRG0_ECAP0_IN_APWM_OUT

PRU-ICSSG Enhanced Capture (ECAP) Input or Auxiliary

PWM (APWM) Output

R2, U5

PRG0_ECAP0_SYNC_IN

PRU-ICSSG ECAP Sync Input

P5, V5

PRG0_ECAP0_SYNC_OUT

PRU-ICSSG ECAP Sync Output

AA4, V5

PRG0_IEP0_EDIO_OUTVALID

PRU_ICSSG Industrial Ethernet Digital I/O Outvalid

C13

PRG0_IEP0_EDC_LATCH_IN0

PRU_ICSSG Industrial Ethernet Distributed Clock Latch

Input

PRG0_IEP0_EDC_LATCH_IN1

PRU_ICSSG Industrial Ethernet Distributed Clock Latch

Input

PRG0_IEP0_EDC_SYNC_OUT0

PRU_ICSSG Industrial Ethernet Distributed Clock Sync

Output

PRG0_IEP0_EDC_SYNC_OUT1

PRU_ICSSG Industrial Ethernet Distributed Clock Sync

Output

AM6442, AM6441, AM6422, AM6421, AM6412, AM6411

SPRSP56J – JANUARY 2021 – REVISED JUNE 2026

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