APM32F103CBT6-R datasheet(34/78 Pages) GEEHY

34 / 78 page

w w w. g e e h y. c o m

P a g e 33

Figure 11 Typical Applications Using 8MHz Crystals

偏置控制增益

CL1

CL2

8MHz

共振器

OSC-IN

OSC-OUT

fHSECLK

5.5.1.2

A low-speed external clock generated using a crystal/ceramic resonator

The low-speed external clock (LSECLK) can be generated using a 32.768 kHz crystal/ceramic

resonator. The following table shows the information of evaluated external devices. In the

applications, the resonator and load capacitor must be as close to the oscillator pins as possible

to reduce distortion and stable time of startup. For detailed parameters (frequency, package,

precision, etc.) of crystal resonator, please consult the corresponding manufacturer

Table20 LSECLK Oscillator Characteristics (fLSECLK =32.768KHz) (1)

Symbol

Parameter

Condition

Minimum

value

Typical

value

Maximum

value

Unit

fOSC_IN

Oscillator frequency

32.768

KHz

Feedback resistance

MΩ

CL1&

CL2(2)

Recommended load

capacitance and

corresponding crystal serial

impedance (RS) (3)

= 30kΩ

LSECLK drive current

VDD=3.3V，

VIN=VSS

0.1

μA

tSU(LSECLK)(4)

Start Time

VDD is stable

2.03

This table is assessment table.

See prompt and warning paragraphs.

A high-quality oscillator with a small RS value (such as MSIV-TIN 32.768kHz) can be selected to

optimize the current consumption. Please consult the crystal manufacturer for details.

tSU(HSECLK) is the startup time, which defines the time when LSECLK is enabled by software to the

time when stable oscillation at 32.768KHz is obtained. This value is measured using a standard

crystal resonator, which may vary greatly due to different crystal manufacturers.

Prompt: It is recommended that high-quality ceramic dielectric capacitors between 5pF and

15pF should be selected for CL1 and CL2, and the capacitance value selected should meet the

requirements of crystals or resonators. Generally, CL1 and CL2 have the same parameters. The

load capacitance parameters usually given by crystal manufacturers are the serial combination

values of CL1 and CL2. The calculation formula of load capacitance CL: CL = CL1 x CL2 / (CL1 +

oscillator

offset control gain

APM32F103CBT6-R bảng dữ liệu(PDF) 34 Page - Geehy Semiconductor Co., Ltd.

APM32F103CBT6-R bảng dữ liệu(HTML) 34 Page - Geehy Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

bảng dữ liệu tải về

Link URL