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©2016-2023 Renesas Electronics Corporation

November 20, 2023

8P34S2108 Datasheet

1.8V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL and other differential signals. The differential input signal must meet both the VPP and VCMR

input requirements. Figure 4 to Figure 6 show interface examples for the CLK /nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver termination requirements.

Figure 4. Differential Input Driven by an LVDS Driver – DC Coupling

Figure 5. Differential Input Driven by an LVDS Driver – AC Coupling

Figure 6. Differential Input Driven by an LVPECL Driver – AC Coupling

 

Zo = 50

R1

100

R2

2.4k

LVDS

1.8V

CLK

nCLK

VREF

C2 0.1uF R3

5k

Zo = 50

VDD

C1 0.1uF

 

Zo = 50

R6

100 - 200

R4

0 - 100

R1

100

R2

2.4k

LVPECL

1.8V

CLK

nCLK

VREF

C2 0.1uF

R7

100 - 200

R3

5k

Zo = 50

R5

0 - 100

2,5V or 3.3V

C1 0.1uF