M36W432T70ZA1T datasheet(21/57 Pages) STMICROELECTRONICS

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M36W432T, M36W432B

Write. Write operations are used to write data to

the SRAM. The SRAM is in Write mode whenever

WS and E1S are at VIL,and E2S is at VIH. Either

the Chip Enable inputs, E1S and E2S, or the Write

Enable input, WS, must be deasserted during ad-

dress transitions for subsequent write cycles.

A Write operation is initiated when E1S is at VIL,

E2S is at VIH and WS is at VIL. The data is latched

on the falling edge of E1S, the rising edge of E2S

or the falling edge of WS, whichever occurs last.

The Write cycle is terminated on the rising edge of

E1S, the rising edge of WS or the falling edge of

E2S, whichever occurs first.

If the Output is enabled (E1S=VIL,E2S=VIH and

GS=VIL), then WS will return the outputs to high

impedance within tWLQZ of its falling edge. Care

must be taken to avoid bus contention in this type

of operation. The Data input must be valid for tD-

VWH before the rising edge of Write Enable, for

tDVE1H before the rising edge of E1S or for tDVE2L

before the falling edge of E2S, whichever occurs

first, and remain valid for tWHDX,tE1HAX or tE2LAX

(see Table 20, Figure 16, 17, 18 and 19).

Standby/Power-Down. The SRAM component

has a chip enabled power-down feature which in-

vokes an automatic standby mode (see Table 19,

Figure 15). The SRAM is in Standby mode when-

ever either Chip Enable is deasserted, E1S at VIH

or E2S at VIL.

Data Retention. The SRAM data retention per-

formances as VDDS goes down to VDR are de-

scribedin Table21and Figure20, 21. InE1S

controlled data retention mode, the minimum

standby

current

mode

entered

when

E1S

≥ VDDS – 0.2V

and

E2S

≤ 0.2V

E2S

≥ VDDS – 0.2V. In E2S controlled data reten-

tion mode, minimum standby current mode is en-

tered when E2S

≤ 0.2V.

Output Disable. The data outputs are high im-

pedance when the Output Enable, GS,is at VIH

with Write Enable, WS,atVIH.

MAXIMUM RATING

Stressing the deviceabove therating listedinthe

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 11. Absolute Maximum Ratings

Note: 1. Depends on range.

Symbol

Parameter

Value

Unit

Min

Max

Ambient Operating Temperature (1)

–40

°C

TBIAS

Temperature Under Bias

–40

125

°C

TSTG

Storage Temperature

–55

155

°C

VIO

Input or Output Voltage

–0.5

VDDQF +0.3

VDDF,VDDQF

Flash Supply Voltage

–0.6

3.9

VPPF

Program Voltage

–0.6

VDDS

SRAM Supply Voltage

–0.5

3.9

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