M36W432T70ZA1T datasheet(7/57 Pages) STMICROELECTRONICS

7 / 57 page

7/57

M36W432T, M36W432B

Flash Write Protect (WPF). Write Protect is an

input that gives an additional hardware protection

for each block. When Write Protect is at VIL,the

Lock-Down is enabled and the protection status of

the block cannot be changed. When Write Protect

is at VIH, the Lock-Down is disabled and the block

can be locked or unlocked. (refer to Table 6, Read

Protection Register and Protection Register Lock).

Flash Reset (RPF). The Reset input provides a

hardware reset of the Flash memory. When Reset

is at VIL, the memory is in reset mode: the outputs

are high impedance and the current consumption

is minimized. After Reset all blocks are in the

Locked state. When Reset is at VIH, the device is

in normal operation. Exiting reset mode the device

enters read array mode, but a negative transition

of Chip Enable or a change of the address is re-

quired to ensure valid data outputs.

SRAM Chip Enable (E1S,E2S). TheChipEn-

able inputs activate the SRAM memory control

logic, input buffers and decoders. E1S at VIH or

E2S at VIL deselects the memory and reduces the

power consumption to the standby level. E1S and

E2S can also be used to control writing to the

SRAM memory array, while WS remains at VIL. It

is not allowed to set EF at VIL, E1S at VIL and E2S

at VIH at the same time.

SRAM WriteEnable(WS). The Write Enable in-

put controls writing to the SRAM memory array.

WS is active low.

SRAM Output Enable (GS). The Output Enable

gates the outputs through the data buffers during

a read operation of the SRAM memory. GS is ac-

tive low.

SRAM Upper Byte Enable (UBS). The

Upper

Byte Enable enables the upper bytes for SRAM

(DQ8-DQ15). UBS is active low.

SRAM Lower Byte Enable (LBS). The

Lower

Byte Enable enables the lower bytes for SRAM

(DQ0-DQ7). LBS is active low.

VDDF Supply Voltage (2.7V to 3.3V). VDDF pro-

vides the power supply to the internal core of the

Flash Memory device. It is the main power supply

for all operations (Read, Program and Erase).

VDDQF and VDDS Supply Voltage (2.7V to 3.3V).

VDDQF provides the power supply for the Flash

memory I/O pins and VDDS provides the power

supply for the SRAM control pins. This allows all

Outputs to be powered independently from the

Flash core power supply, VDDF.VDDQF canbetied

to VDDS

VPPF Program Supply Voltage. VPPF is both a

control input and a power supply pin for the Flash

memory. The two functions are selected by the

voltage range applied to the pin. The Supply Volt-

age VDDF and the Program Supply Voltage VPPF

can be applied in any order.

If VPPF is kept in a low voltage range (0V to 3.6V)

VPPF is seen as a control input. In this case a volt-

age lower than VPPLK gives an absolute protection

against program or erase, while VPPF >VPPLK en-

ables these functions (see Table 14, DC Charac-

teristics for the relevant values). VPPF is only

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

If VPPF is in the range 11.4V to 12.6V it acts as a

power supply pin. In this condition VPPF must be

stable until the Program/Erase algorithm is com-

pleted (see Table 16 and 17).

VSSF and VSSS Ground. VSSF and VSSS are the

ground reference for all voltage measurements in

the Flash and SRAM chips, respectively.

Note: Each device in a system should have VD-

DF,VDDQF and VPPF decoupled with a 0.1µF ca-

pacitor close to the pin. See Figure 9, AC

Measurement Load Circuit. The PCB trace

widths should be sufficient to carry the re-

quired VPPF program and erase currents.

M36W432T70ZA1T bảng dữ liệu(PDF) 7 Page - STMicroelectronics

M36W432T70ZA1T bảng dữ liệu(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

bảng dữ liệu tải về

Link URL