KMB-001LEVALZ datasheet(25/33 Pages) RENESAS

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ISLA224P12

FN7983 Rev.4.01

Page 25 of 32

Apr 8, 2024

This register is not changed by a Soft Reset.

ADDRESS 0X74: OUTPUT_MODE_B

Bit 6 DLL Range

This bit sets the DLL operating range to fast (default) or slow.

Internal clock signals are generated by a delay-locked loop (DLL),

which has a finite operating range. Table 13 shows the allowable

sample rate ranges for the slow and fast settings.

ADDRESS 0XB6: CALIBRATION STATUS

The LSB at address 0xB6 can be read to determine calibration

status. The bit is ‘0’ during calibration and goes to a logic ‘1’

when calibration is complete. This register is unique in that it can

be read after POR at calibration, unlike the other registers on

chip, which can’t be read until calibration is complete.

DEVICE TEST

The ISLA224P12 can produce preset or user defined patterns on

the digital outputs to facilitate in-situ testing. A user can pick

from preset built-in patterns by writing to the output test mode

field [7:4] at 0xC0 or user defined patterns by writing to the user

test mode field [2:0] at 0xC0. The user defined patterns should

be loaded at address space 0xC1 through 0xD0, see the “SPI

Memory Map” on page 27 for more detail. The predefined

patterns are shown in Table 14. The test mode is enabled

asynchronously to the sample clock, therefore several sample

clock cycles may elapse before the data is present on the output

bus.

ADDRESS 0XC0: TEST_IO

Bits 7:4 Output Test Mode

These bits set the test mode according to Table 14. Other

values are reserved. User test patterns loaded at 0xC1 through

0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a

pattern depth value to [2:0] at 0xC0. See the “SPI Memory

Map” on page 27.

Bits 2:0 User Test Mode

The three LSBs in this register determine the test pattern in

combination with registers 0xC1 through 0xD0. Refer to the

“SPI Memory Map” on page 27.

ADDRESS 0XC1: USER_PATT1_LSB

ADDRESS 0XC2: USER_PATT1_MSB