KMB-001LEVALZ datasheet(20/33 Pages) RENESAS

20 / 33 page

ISLA224P12

FN7983 Rev.4.01

Page 20 of 32

Apr 8, 2024

For clock divide settings > ‘1’, the absolute phase of the output

clocks for multiple A/Ds is indeterminate - there will be a phase

ambiguity between the output clocks of ADCs in a multiple ADC

system. The CLKDIVRST feature allows the phase of multiple

A/Ds to be synchronized (see Figure 37) when the internal clock

divider is used, greatly simplifying data capture in systems

employing multiple A/Ds. For clock divide setting = ’1’, there is

no phase ambiguity between clock outputs in a multiple ADC

system and CLKDIVRST can be left as a DNC (do not connect)

The CLKDIVRST signal must be well-timed with respect to the

sample clock (see “Switching Specifications” on page 11).

Figure 37 shows assertion of CLKDIVRSTP by a positive edge

(CLKDIVRSTN must be driven but is not shown); CLKDIVRSTP can

remain high indefinitely after a synchronization event.

CLKDIVRSTP can also be a pulse if needed, with CLKDIVRSTP

returning to a logic ‘0’ after assertion; in this case the CLKDIVRST

pulse width should be a minimum of 3 input sample clock

periods. In applications where multiple CLKDIVRST pulse events

are required, a user should wait a minimum of 30 clock cycles

before starting a second CLKDIVRST pulse event.

It will take a maximum of 30 input clock cycles to attain

synchronization (tRSTRT) in applications where the input clock is

not interrupted; if the input clock is interrupted CLKOUT will be

static or indeterminate until synchronization is attained.

In some applications, interrupting the input sample clock briefly

(~ 150 cycles max) can simplify the timing requirements for

synchronization using CLKDIVRST), in this case the total

CLKDIVRST recovery time will increase by the number of input

clock cycles the sample clock is held static. Valid data is

available (after recovery) in all cases after the normal pipeline

latency.

Application Note AN1604 describes the synchronization of

multiple ISLA1xxP50s. This document discusses the topic of

synchronization in more detail and can be used to better

understand the ISLA2XXPxx ADCs’ operation.

FIGURE 37. SYNCHRONOUS RESET OPERATION

CLKDIVRSTP

ADC1 OUTPUT DATA

ADC1 CLKOUTP

ADC2 CLKOUTP

(phase 1)

ADC2 CLKOUTP

(phase 2)

L+td

tRSTH

tRSTS

tRSTRT

ADC2 OUTPUT DATA

ANALOG INPUT

SAMPLE CLOCK

INPUT

(CLKDIV = 2)

NOTES:

14. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.

15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.

CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.

16. Either Output Clock Phase (Phase 1 or Phase 2 ) equally likely prior to synchronization.

(Note 16)

(Note 15)

(Note 14)

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