STW81103 datasheet(25/53 Pages) STMICROELECTRONICS

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STW81103

Circuit description

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5.9

Output stage

The differential output signal of the synthesizer can be selected by software among three

different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability.

The selection of the output stage is done by programming properly the PD[4:0] bits.

The output stage is an open-collector structure which is able to meet different requirements

over the desired output frequency range by proper connections on the PCB. Refer to

Section 8: Application information for more details on PCB connections.

5.9.1

Output buffer control mode

This control mode allows to enable/disable the output stage by a hardware control pin

(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very

fast switching time is achieved.

This feature can be useful in designing a ping-pong architecture saving the cost of an

external RF switch.

The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in

Table 10.

Table 9.

VCO B performances vs. amplitude setting (Freq = 4.7 GHz)

PLL_A[1:0]

Differential

voltage swing (Vp)

Current

consumption (mA)

PN at 1 MHz

(dBc/Hz)

1.1

-121

1.3

-122

1.9

-126

2.1

-127

Table 10.

EXT_PD pin function setting

OUTBUF_CTRL_EN

Function of the EXT_PD pin

EXT_PD pin settings

Device hardware power down

EXT_PD = 0 V

Device ON

EXT_PD = 3.3 V

Device OFF

Output Buffer control

EXT_PD = 0 V

Output Stage ON

EXT_PD = 3.3 V

Output Stage OFF

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