STW81103 datasheet(12/53 Pages) STMICROELECTRONICS

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Electrical specifications

STW81103

12/53

External VCO

Frequency range

0.625

5.0

GHz

Input level

-10

dBm

Current consumption

VCO internal buffer

PLL miscellaneous

IPLL

Current consumption

Input buffer, prescaler, digital

dividers, misc.

tlock

Lockup time(5) (7)

25 kHzPLLbandwidth; within

1 ppm of frequency error

150

μs

In order to achieve best phase noise performance 1 V peak level is suggested.

The frequency step is related to the PFD input frequency as follows:

- Fstep = FPFD for direct output

- Fstep = FPFD/2 for divided by 2 output

- Fstep = FPFD/4 for divided by 4 output

See relationship between ICP and REXT in

Section 5.7: Charge pump.

The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop

BW.

Guaranteed by design and specification.

When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range

for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating

temperature range (-40

° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in

either direction) is within the limit specified by

ΔT

LK, provided that the final temperature T1 is still inside the nominal range.

If higher

ΔT are required the ”VCO calibration auto-restart“ feature can be enabled, thus allowing to re-start the VCO

calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).

Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with

FPFD=400 kHz).

Table 5.

Electrical specifications (continued)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

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