W77C32 datasheet(23/78 Pages) WINBOND

23 / 78 page

W77C32/W77C032A

Publication Release Date: February 1, 2007

- 23 -

Revision A8

TF2:

Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count

is equal to the capture register in down count mode. It can be set only if RCLK and TCLK

are both 0. It is cleared only by software. Software can also set or clear this bit.

EXF2:

Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow

will cause this flag to set based on the CP/RL2, EXEN2 and DCEN bits. If set by a

negative transition, this flag must be cleared by software. Setting this bit in software or

detection of a negative transition on T2EX pin will force a timer interrupt if enabled.

RCLK:

Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data

in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation,

otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator

mode.

TCLK:

Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting

data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud

rate clock, otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate

generator mode.

EXEN2:

Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if

Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin

will be ignored, otherwise a negative transition detected on the T2EX pin will result in

capture or reload.

TR2:

Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will

halt the timer 2 and preserve the current count in TH2, TL2.

C/ T2 :

Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a

counter. Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate

generator mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on

T2M bit (CKCON.5), otherwise it will count negative edges on T2 pin.

CP/ RL2 : Capture/Reload Select. This bit determines whether the capture or reload function will be

used for timer 2. If either RCLK or TCLK is set, this bit will be ignored and the timer will

function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will

occur when timer 2 overflows or a falling edge is detected on T2EX pin if EXEN2 = 1.

If this bit is 1, then timer 2 captures will occur when a falling edge is detected on T2EX pin if

EXEN2 = 1.

7.2 Timer 2 Mode Control

Bit:

HC5

HC4

HC3

HC2

T2CR

T2OE

DCEN

Mnemonic: T2MOD

Address: C9h

HC5:

Hardware Clear INT5 flag. Setting this bit allows the flag of external interrupt 5 to be

automatically cleared by hardware while entering the interrupt service routine.

HC4:

Hardware Clear INT4 flag. Setting this bit allows the flag of external interrupt 4 to be

automatically cleared by hardware while entering the interrupt service routine.

HC3:

Hardware Clear INT3 flag. Setting this bit allows the flag of external interrupt 3 to be

automatically cleared by hardware while entering the interrupt service routine.

HC3:

Hardware Clear INT2 flag. Setting this bit allows the flag of external interrupt 3 to be

automatically cleared by hardware while entering the interrupt service routine.

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