W77C32 datasheet(22/78 Pages) WINBOND

22 / 78 page

W77C32/W77C032A

- 22 -

Status Register

Bit:

HIP

LIP

XTUP

SPTA1

SPRA1

SPTA0

SPRA0

Mnemonic: STATUS

Address: C5h

HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

LIP:

Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

XTUP: Crystal Oscillator Warm-up Status. When set, this bit indicates CPU has detected clock to be

ready. Each time the crystal oscillator is restarted by exit from power down mode or the

XTOFF bit is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When

this bit is cleared, it prevents software from setting the XT/ RG bit to enable CPU operation

from crystal oscillator.

SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data.

It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,

CD1 will be ignored when this bit is set to 1 and SWB = 1.

SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It

is cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0,

CD1 will be ignored when this bit is set to 1 and SWB = 1.

SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data.

It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1

will be ignored when this bit is set to 1 and SWB = 1.

SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It

is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1

will be ignored when this bit is set to 1 and SWB = 1.

Timed Access

Bit:

TA.7

TA.6

TA.5

TA.4

TA.3

TA.2

TA.1

TA.0

Mnemonic: TA

Address: C7h

TA:

The Timed Access register controls the access to protected bits. To access protected bits, the

user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.

Now a window is opened in the protected bits for three machine cycles, during which the user

can write to these bits.

Timer 2 Control

Bit:

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/ T2

CP/ RL2

Mnemonic: T2CON

Address: C8h

W77C32 bảng dữ liệu(PDF) 22 Page - Winbond

W77C32 bảng dữ liệu(HTML) 22 Page - Winbond

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

bảng dữ liệu tải về

Link URL