TMS320DM643 datasheet(109/162 Pages) TI

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† For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising

edge (to shift data in).

‡ For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling

edge (to shift data in).

B0 B1

A30 A31

B30 B31 C0

C1 C2

C31

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

ACLKR/X (CLKRP = CLKXP = 0)‡

ACLKR/X (CLKRP = CLKXP = 1)†

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

Figure 5-36. McASP Output Timings

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DM643 Peripheral Information and Electrical Specifications

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