TMS320DM643 datasheet(95/162 Pages) TI

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AECLKOUTx

ACEx

ABE[7:0]

AEA[12:3]

AED[63:0]

AEA13

AAOE/ASDRAS/ASOE(A)

AARE/ASDCAS/ASADS/ASRE(A)

AAWE/ASDWE/ASWE(A)

AEA[22:14]

BE1

BE2

BE3

BE4

Bank

Column

READ

APDT(B)

AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,

respectively, during SDRAM accesses.

APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For APDT read,

data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to

the data phase of a read transaction. The latency of the APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01,

10, or 11, respectively. PDTRL equals 00 (zero latency) in this figure.

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269C – FEBRUARY 2005 – REVISED JANUARY 2007

Figure 5-24. SDRAM Read Command (CAS Latency 3) for EMIFA

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DM643 Peripheral Information and Electrical Specifications

TMS320DM643 bảng dữ liệu(PDF) 95 Page - Texas Instruments