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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SN75DP129RHHTG4 bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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SN75DP129RHHTG4 bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 28 page  www.ti.com TMDS and Main Link Pins ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS SN75DP129 SLAS583A – JANUARY 2008 – REVISED MARCH 2008 The main link inputs are designed to be compliant with the DisplayPort 1.1 specification. The TMDS outputs of the SN75DP129 are designed to be compliant with the Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) specifications. The differential output voltage swing can be fine-tuned with the VSadj (TMDS-compliant Voltage Swing Control) resistor. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Single-ended HIGH level output voltage AVCC–10 AVCC+10 mV VOL Single-ended LOW level output voltage AVCC–600 AVCC–400 mV VSWING Single-ended output voltage swing 400 600 mV AVCC = 3.3 V, RT = 50 Ω Change in steady-state common-mode VOC(SS) –5 5 mV output voltage between logic states VOD(PP) Peak-to-peak output differential voltage 800 1200 mV AVCC = 3.3 V, RT = 50 Ω, V(O)SBY Single-ended standby output voltage AVCC–10 AVCC+10 mV LP = 0 0 V ≤ VCC ≥ 1.5 V, AVCC = 3.3 V, I(O)OFF Single-ended power down output current –10 10 µA RT = 50 Ω IOS Short circuit output current VID = 500 mV –15 15 mA RINT Input termination impedance 45 50 55 Ω Vterm Input termination voltage 1 2 V over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time 250 350 600 ps tPHL Propagation delay time 250 350 600 ps tR Rise time 60 90 140 ps tF Fall time AVCC = 3.3 V, RT = 50 Ω, f = 1 MHz 60 90 140 ps tSK(P) Pulse skew 8 15 ps tSK(D) Intra-pair skew 20 40 ps tSK(O) Inter-pair skew 20 65 ps tJITD(PP) Peak-to-peak output residual data jitter AVCC = 3.3 V, RT = 50 Ω, dR = 2.5 Gbps 14 50 ps tJITC(PP) Peak-to-peak output residual clock jitter AVCC = 3.3 V, RT = 50 Ω, f = 250 MHz 8 30 ps 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN75DP129 |
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