MSP3400C datasheet(17/73 Pages) MICRONAS

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MSP 3400C

PRELIMINARY DATA SHEET

MICRONAS INTERMETALL

Table 5–3: Control Register

Name

14..0

CONTROL

RESET

5.1. Protocol Description

Write to DFP or Demodulator Part (long protocol)

daw

Wait

ACK

sub-addr

ACK

addr-byte

high

ACK

addr-byte low

ACK

data-byte high

ACK

data-byte low

ACK

Read from DFP Part (long protocol)

daw

Wait

ACK

sub-addr

ACK

addr-byte

high

ACK

addr-byte

low

ACK

dar

Wait

ACK

data-byte

high

ACK

data-byte

low

NAK

Write to Control / Test / AGC / PLL_Cap Registers (short protocol)

daw

Wait

ACK

sub-addr

ACK

data-byte high

ACK

data-byte low

ACK

Read from Control / Test / AGC / PLL_Cap Registers (short protocol)

daw

Wait

ACK

sub-addr

ACK

dar

Wait

ACK

data-byte high

ACK

data-byte low

NAK

Note: S =

I2C-Bus Start Condition from master

P =

I2C-Bus Stop Condition from master

daw =

Device Address Write

dar =

Device Address Read

ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey)

or master (= CCU, hatched)

NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate

‘End of Read’ or from MSPC indicating internal error state (not illustrated)

Wait = I2C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms)

Fig. 5–1: I2C bus protocol

I2C_DA

I2C_CL

(MSB first; data must be stable while clock is high)

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