M25P10-AVMB3TSLASHY datasheet(23/51 Pages) NUMONYX

23 / 51 page

M25P10-A

Instructions

23/51

Regardless of the order of the two events, the Hardware Protected mode (HPM) can be

entered:

●

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

●

or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the Hardware Protected mode (HPM) can

never be activated, and only the Software Protected mode (SPM), using the Block Protect

(BP1, BP0) bits of the Status Register, can be used.

Figure 11.

Write Status Register (WRSR) instruction sequence

Table 7.

Protection modes

signal

SRWD

bit

Mode

Write protection of the

Status Register

Memory content

Protected area(1)

As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

Unprotected

area(1)

Software

protected

(SPM)

Status Register is writable (if

the WREN instruction has set

the WEL bit)

The values in the SRWD, BP1

and BP0 bits can be changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program

and Sector Erase

instructions

Hardware

protected

(HPM)

Status Register is hardware

write protected

The values in the SRWD, BP1

and BP0 bits cannot be

changed

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program

and Sector Erase

instructions

AI02282D

3456789 10 11 12 13 14 15

High Impedance

Instruction

Status

765432

MSB

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