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LAN8808D/KDX bảng dữ liệu(PDF) 70 Page - Microchip Technology

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LAN8808D
DS00005833C-page 70
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6.6.7
GPIO TIMING
This section specifies the general GPIO timing of the device.
Note 6-19
GPIOs must have pulse widths with a minimum of two 125 MHz clocks, but no synchronous timing
relationship is specified. GPIOs configured as alternate functions may have synchronous timing
relationships.
6.6.8
GPIO SOF DETECTION TIMING
This section specifies the GPIO SOF timing of the device.
Note 6-20
8 ns for 1000BASE-T operation, 40 ns for 100BASE-TX operation, 400 ns for 10BASE-T operation.
TABLE 6-16:
GPIO TIMING VALUES
Symbol
Description
Min
Typ
Max
Unit
tinput_pulse
GPIO input pulse width
18
—
—
ns
toutput_pulse
GPIO output pulse width
14
—
—
ns
tinput_su
GPIO input setup/hold timing
N/A, treat as asynchronous (Note 6-19)
toutput_hold
GPIO output valid/hold timing
N/A, treat as asynchronous (Note 6-19)
FIGURE 6-7:
GPIO SOF TIMING
TABLE 6-17:
GPIO SOF TIMING VALUES
Symbol
Description
Min
Typ
Max
Unit
trx_sof_lat
RX SOF latency
1000M
100M
10M
—472
456
7696
—ns
trx_sof
RX SOF pulse width
—
Note 6-20
—ns
trx_sof_skew
RX SOF skew between GPIOs
—
0.5
1
ns
ttx_sof_lat
TX SOF latency
1000M
100M
10M
—59
150
645
—ns
ttx_sof
TX SOF pulse width
—
Note 6-20
—ns
ttx_sof_skew
TX SOF skew between GPIOs
—
0.5
1
ns
trx_sof_lat
GPIOs
RX +/-
trx_sof_skew
GPIOs
TX +/-
ttx_sof_skew
ttx_sof_lat



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