LAN8808DSLASHKDX datasheet(18/80 Pages) MICROCHIP

18 / 80 page

LAN8808D

DS00005833C-page 18

Reference Clock

Select

REF_CLK_SEL1

VIS

This pin controls reference clock selection of the System PLL

and QSGMII SerDes MPLL.

0: SYSPLL and QSGMII both reference 25 MHz (single-ended

external reference) from XI (not recommended)

1: SYSPLL and QSGMII both reference 125 MHz (differential

external reference) from CK125_REF_INP/M (recommended

for best QSGMII performance)

Note:

This is a live pin, not a configuration strap, and must

be permanently tied high/low.

Note:

XI is a 25 MHz external clock. CK125_REF_INP/M

is a 125 MHz external clock.

SerDes Bias

Resistor

RES_REF

This pin must be connected to ground through a 200Ω 1%

100 ppm/

C resistor.

PHY Bias Resistor

ISET

This pin must be connected to ground through a 6.04 kΩ 1%

resistor.

Test Mode

TEST_MODE

VIS

For normal operation, this pin must be pulled-down to ground.

TABLE 3-6:

JTAG PINS

Name

Symbol

Buffer

Type

Description

JTAG Mux Select

TMS

SRL

JTAG test mode select

JTAG Clock

TCK

SRL

JTAG test clock

JTAG Data Input

TDI

SRL

JTAG data input

JTAG Data

Output

TDO

SRL

JTAG data output

TABLE 3-7:

CONFIGURATION STRAP INPUT PINS

Name

Symbol

Buffer

Type

Description

PHY Base

Address

Configuration

Straps

PHYAD[4:0]

VIS

Configures the PHY Management base address, used with

MDIO bus transactions. The PHY base address, PHYAD[4:0],

is sampled and latched at power-up/reset and is configurable

to any value from 0 to 1Fh. Each PHY address bit is configured

as follows:

Pulled-up = 1

Pulled-down = 0

The addresses of each of the 4 PHYs are the base value, as

defined by PHYAD[4:0], plus offsets of 0, 1, 2 and 3. Refer to

Section 3.3.2, "PHY Address (PHYAD[4:0])" for additional

information.

Note:

PHYAD[4:0] must never be greater than ‘h1C.

TABLE 3-5:

MISCELLANEOUS PINS (CONTINUED)

Name

Symbol

Buffer

Type

Description

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