LAN8818DSLASHKDX datasheet(60/101 Pages) MICROCHIP

60 / 101 page

LAN8818D

DS00005832C-page 60

5.17

Interrupts

The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status

update in the device. The Interrupt Enable register contains the interrupt control bits that enable and disable the condi-

tions for asserting the INT_N signal. The Interrupt Status register contains the interrupt status bits that indicate which

interrupt conditions have occurred. Most interrupt status bits are cleared upon reading. Some bits are read only and

have a lower level register to indicate individual sources.

The interrupt structure of the device is detailed in Figure 5-14.

The INT_N buffer type is selectable between open-drain and push-pull and is configured by the INT Buffer Type field in

the Output Control register. The default is open-drain.

The Intr Polarity Invert bit in the Control register sets the interrupt level to active high or active low. The default is active

low. If the buffer type is set to open-drain, the polarity is forced to be active low.

Note:

Bits in the Interrupt Status register are set by the interrupt events regardless of the value of the correspond-

ing bits in the Interrupt Enable register.

FIGURE 5-14:

INTERRUPT STRUCTURE

Interrupt

Sources

Logical

1588_TSU_x

Interrupt

1588 Timestamp Engine x

INT_N

Chip-Level

Interrupt

Chip-Level

Interrupt Status Register

GPHY_Hard_Macro_x

Interrupt

1588 Common Logic

Interrupt

1588

Interrupt

Enable

Logical

GPHY Hard Macro x

GPHY

Interrupt

Enable

Logical

PTP Common

Interrupt

Enable

GPIOs

Interrupt

Logical

GPIO

Interrupt

Enable

AB PVT

Interrupt

Logical

AB PVT

Interrupt

Mask

1588 ISR

Interrupt

Sources

GPHY ISR

Interrupt

Sources

PTP Common ISR

Interrupt

Sources

GPIO ISR

Interrupt

Sources

AB PVT ISR

1588 Common Logic

GPIOs

Temperature Monitor

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