LAN8804D datasheet(29/89 Pages) MICROCHIP

29 / 89 page

LAN8804D

DS00003591K-page 29

The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/

5B decoder. Finally, the NRZ serial data is converted to the MII/GMII or Reduced Gigabit Media Independent Interface

format and provided as the input data to the MAC.

5.1.3

SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)

and baseline wander. Transmitted data is scrambled using an 11-bit wide Linear Feedback Shift Register (LFSR). The

scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream

using the same sequence as at the transmitter.

5.1.4

10BASE-T TRANSMIT

The 10BASE-T output drivers are incorporated into the 100BASE-TX drivers to allow for transmission with the same

magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with typical amplitude of

2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-T/

10BASE-Te signals have harmonic contents that are at least 31 dB below the fundamental frequency when driven by

an all-ones Manchester-encoded signal.

5.1.5

10BASE-T RECEIVE

On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a

Phase-Locked Loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths to prevent

noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks

onto the incoming signal and the device decodes a data frame. The receiver clock is maintained active during idle peri-

ods between receiving data frames.

The device removes all 7 bytes of the preamble and presents the received frame starting with the Start of Frame Delim-

iter (SFD) to the MAC.

Auto-polarity correction is provided for the receiving differential pair to automatically swap and fix the incorrect ± polarity

wiring in the cabling.

5.2

1000BASE-T Transceiver

The 1000BASE-T transceiver is based on a mixed-signal/digital-signal processing (DSP) architecture, which includes

the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, preci-

sion clock recovery scheme, and power-efficient line drivers.

5.2.1

ANALOG ECHO-CANCELLATION CIRCUIT

In 1000BASE-T mode, the analog echo-cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit

relieves the burden of the ADC and the adaptive equalizer.

This circuit is disabled in 10BASE-T/100BASE-TX mode.

5.2.2

AUTOMATIC GAIN CONTROL (AGC)

In 1000BASE-T mode, the AGC circuit provides initial gain adjustment to boost up the signal level. This pre-conditioning

circuit is used to improve the signal-to-noise ratio of the receive signal.

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