PL133-37

Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 02/24/15 Page 2

PIN DESCRIPTION

Name

Package Pin #

Type

Description

SOT23-6L

CLK1

1

O

Output clock

GND

2

P

Ground connection

FIN

3

I

Reference clock input

CLK0

4

O

Output clock

VDD

5

P

Power supply

CLK2

6

O

Output clock

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper termi-

nation this will cause reflections (looks like ringing).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply Considerations

- Place decoupling capacitors as close as possible to

the VDD pin(s) to limit noise from the power supply

- Multiple VDD pins should be decoupled separately

for best performance.

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency de-

pendant. Typical value to use is 0.1µF.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

(Typical buffer impedance 20Ω)

To CMOS Input

Series Resistor

Use value to match output buffer impedance to

50Ω trace. Typical value 30Ω

50Ω line