BD9DA00MF datasheet(25/53 Pages) ROHM

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BD9DA00MF

Datasheet

TSZ02201-0J2J0AB01940-1-2

18.Mar.2025 Rev.001

www.rohm.com

TSZ22111 • 15 • 001

2. Protection – continued

(2) Low-Side Reverse Over Current Protection (ROCP)

While Low-Side FET is ON in the Forced CCM setting, if the inductor current exceeds the reverse detection current

IROCP = 6.5 A (Typ), Low-Side FET is turned OFF and High-Side FET is turned ON.

(3) Under Voltage Lockout Protection (UVLO)

The device shuts down when the input voltage VIN falls to 1.85 V (Typ) or less, or VCC voltage VCC is 2.5 V (Typ) or

less. It starts up when VIN becomes 2.4 V (Typ) or more and VCC becomes 2.8 V (Typ) or more. The hysteresis is 550

mV (Typ) and 300 mV (Typ), respectively.

VIN

VCC

VINUVLO2

VCCUVLO1

VCCUVLO2

UVLO

VOUT

2.4 V (Typ)

2.8 V (Typ)

2.5 V (Typ)

3.0 V (Typ)

tSS

VINUVLO1

1.85 V (Typ)

Figure 44. UVLO Timing Chart

(4) Thermal Shutdown Protection (TSD)

The thermal shutdown circuit prevents heat damage to the IC. If the junction temperature (Tj) exceeds the TSD

detection temperature (175 °C, Typ), the output MOSFETs are turned off. When the Tj falls below the TSD release

temperature (150 °C, Typ), the IC restarts up with soft start. The input voltage required for the restart is the same as

that for the initial startup (Input voltage 4.0 V or more). Note that the TSD circuit operates in a situation that exceeds

the absolute maximum ratings. Therefore, under no circumstances, should the TSD circuit be used in a set design or

for any purpose other than protecting the IC from heat damage.

(5) Over Voltage Protection (OVP)

The overvoltage protection (OVP) is enabled after the SS/REF pin voltage reaches 0.6 V (Typ). OVP function operates

when the FB pin voltage VFB becomes 116 % (Typ) or more of the FB reference voltage VREF, and it depends on the

device operation mode.

During Forced CCM mode operation, after the device detects OVP, it latches off the High-Side FET and turns on the

Low-Side FET. However, when the current flowing through the Low-Side FET reaches reverse detection current IROCP,

the Low-Side FET is temporarily turned off and the High-Side FET is turned on for an ONTIME determined by the

input/output status. After that, the Low-Side FET returns to the latched-on state.

During LLM mode operation, after the device detects OVP, it turns off the High-Side FET and turns on the Low-Side

FET. When the Low-Side FET turns on, the output voltage decreases, and if VFB falls below 50% (Typ) of VREF, both

the High-Side FET and Low-Side FET latch off. However, before VFB falls below 50 % (Typ) of VREF, when the current

flowing through the Low-Side FET reaches IROCP, the Low-Side FET is temporarily turned off and the High-Side FET is

turned on for an ONTIME determined by the input/output status. After that, the Low-Side FET returns to the on state.

The device repeats this operation until VFB is less than 50 % (Typ) of VREF.

During both Forced CCM and LLM mode operation, the device resets the latched state by toggling EN or by detecting

VIN UVLO or VCC UVLO.

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