+5 V LINEAR REGULATOR & +3.3 V REFERENCE VOLTAGE GENERATOR

This low drop-out regulator powers almost all the internal circuitry, that is the +3.3V reference voltage

generator, amplifiers, comparators, digital logic, and MOSFET drivers. Its output is externally available

through pin REG5.

The typical external use of this generator is to charge the bootstrap capacitors used to produce the gate-

drive voltage for the high-side MOSFET’s of both PWM converters.

At start-up and when the 5V section is not operating, this regulator is powered by the chip input voltage.

To reduce power consumption, the linear regulator is turned off and the REG5 pin is internally connected

to the 5V PWM regulator output via V5SW pin, when the 5V PWM regulator is active and its output volt-

age is above the switchover threshold, 4.5V.

The 5V regulator is always active, even if both PWM regulators are disabled, as long as power is applied

to the chip.

The 3.3V reference voltage generator, which is active only when either PWM converter is enabled, pro-

vides comparison levels for threshold detection and device operation. It is allowed to source up to 5mA

to an external load from its buffered output, externally available through pin VREF.

If either REG5 or VREF does not deliver the correct voltage, the device is shut down.

POWER MANAGEMENT

The L4992 is provided with some control pins suitable to perform some functions which are commonly

used or sometimes required in battery-operated equipment. Besides, it features controlled timing se-

quences in case of turn-on/off and device shutdown for a safe and reliable behaviour under all condi-

tions.

As above mentioned, RUN3 and RUN5 pins allow to disable separately both PWM converters by means

of logic signals (likely coming from a

µP) as mentioned earlier.

NOSKIP can disable the pulse-skipping feature: when it is held high neither of the PWM regulators is al-

lowed to enter this kind of operation.

The PWROK output signal drives low immediately when either PWM regulator output falls below its own

undervoltage threshold or when either of them is disabled. It is high when both regulator run properly.

A capacitor connected between CRST and ground fixes a time, in the order of 2ms/nF, which delays the

transition low-high of PWROK. This happens at start-up or after recovering an undervoltage condition,

provided both RUN3 and RUN5 are high. The delay starts from the moment in which the output voltage

has reached its correct value for both sections.

The same delay intervenes also in another circumstance: when a section is disabled (because its RUN is

driven low or owing to a thermal shutdown), the relevant synchronous rectifier is turned on after the

above delay in order to make sure that the load is no longer supplied.

This delay, however, does not intervene in case of overvoltage: the synchronous rectifier is immediately

turned on after the shutdown, thus acting as a built-in "crowbar".

All these timing sequences are illustrated in Fig 7.

DETAILED FUNCTIONAL DESCRIPTION (continued)

L4992

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