CY28301PVC datasheet(12/13 Pages) SPECTRALINEAR

12 / 13 page

CY28301

Rev 1.0, November 27, 2006

Page 12 of 13

PCI

TPeriod

PCI CLK Period

30.0

N/A

30.0

N/A

30.0

N/A

4, 7

THIGH

PCI CLK High Time

12.0

N/A

12.0

N/A

12.0

N/A

TLOW

PCI CLK Low Time

12.0

N/A

12.0

N/A

12.0

N/A

TRISE

PCI CLK Rise Time

0.5

2.0

0.5

2.0

0.5

2.0

TFALL

PCI CLK Fall Time

0.5

2.0

0.5

2.0

0.5

2.0

tpZL, tpZH

Output Enable Delay (All outputs)

1.0

10.0

1.0

10.0

1.0

10.0

tpLZ, tpZH

Output Disable Delay

(All outputs)

1.0

10.0

1.0

10.0

1.0

10.0

tstable

All Clock Stabilization from

Power-Up

AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5% fXTL = 14.31818 MHz)

Parameter

Description

66.6-MHz Host

100-MHz Host

133-MHz Host

Unit

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Group Skew and Jitter Limits

Output Group

Pin-Pin Skew Max.

Cycle-Cycle Jitter

Duty Cycle

Nom. VDD

Skew, Jitter

Measure Point

CPU

175 ps

250 ps

45/55

2.5V

1.25V

SDRAM

250 ps

45/55

3.3V

1.5V

APIC

250 ps

500 ps

45/55

2.5V

1.25V

48MHz

250 ps

500 ps

45/55

3.3V

1.5V

3V66

175 ps

500 ps

45/55

3.3V

1.5V

PCI

500 ps

45/55

3.3V

1.5V

REF

N/A

1000 ps

45/55

3.3V

1.5V

Clock Output Wave

2.5V Clocking

3.3V Clocking

Test Point

Test Load

TPERIOD

Duty Cycle

THIGH

2.0

1.25

0.4

TLOW

TRISE

TFALL

TLOW

TRISE

TFALL

TPERIOD

Duty Cycle

THIGH

2.4

1.5

0.4

Output

Buffer

Interface

Figure 1. Output Buffer

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