LPC3240 datasheet(28/80 Pages) NXP

28 / 80 page

LPC3220_30_40_50

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Product data sheet

Rev. 2.1 — 24 June 2014

28 of 80

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

7.4 Internal memory

7.4.1 On-chip ROM

The built-in 16 kB ROM contains a program which runs a boot procedure to load code

from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory,

or NAND FLASH.

After reset, execution always begins from the internal ROM. The bootstrap software first

reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot

and can download a program over serial link UART 5 to IRAM and transfer execution to

the downloaded code.

If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot

process first tests SPI memory for boot information if present it uploads the boot code and

transfers execution to the uploaded software. If the SPI is not present or no software is

loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code

and if present boots from static memory, If this test fails the boot loader will test external

NAND flash for boot code and boot if code is present.

The boot loader consumes no user memory space because it is in ROM.

7.4.2 On-chip SRAM

On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed

as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM.

7.5 External memory interfaces

The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash

controllers, Secure Digital Memory Controller, and an external memory controller for

SDRAM, DDR SDRAM, and Static Memory devices.

7.5.1 NAND flash controllers

The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell

NAND flash devices and one for single-level cell NAND flash devices. The two NAND

flash controllers use the same pins to interface to external NAND flash devices, so only

one interface is active at a time.

7.5.1.1

Multi-Level Cell (MLC) NAND flash controller

The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash

devices. An external NAND flash device is used to allow the bootloader to automatically

load a portion of the application code into internal SRAM for execution following reset.

The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages.

Programmable NAND timing parameters allow support for a variety of NAND flash

devices. A built-in Reed-Solomon encoder/decoder provides error detection and

correction capability. A 528 byte data buffer reduces the need for CPU supervision during

loading. The MLC NAND flash controller also provides DMA support.

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