This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

10

EN25F80

Rev. E, Issue Date: 2007/11/23

Figure 6. Write Disable Instruction Sequence Diagram

Read Status Register (RDSR) (05h)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status

Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in

progress. When one of these cycles is in progress, it is recommended to check the Write In

Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the

Status Register continuously, as shown in Figure 7.

Figure 7. Read Status Register Instruction Sequence Diagram

Table 6. Status Register Bit Locations

S7

S6

S5

S4

S3

S2

S1

S0

SRP

0

0

BP2

BP1

BP0

WEL

WIP

Note : In OTP mode, SRP bit is served as OTP_LOCK bit.

Status Register Protect

Reserved Bits

Block Protect Bits

Write Enable Latch

Write In Progress