This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

16

EN25F80

Rev. E, Issue Date: 2007/11/23

Chip Erase (CE) (C7h/60h)

The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write Enable Latch (WEL).

The Chip Erase (CE) instruction is entered by driving Chip Select (CS#) Low, followed by the

instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 14. Chip Select (CS#) must be driven High after the

eighth bit of the instruction code has been latched in, otherwise the Chip Erase instruction is not

executed. As soon as Chip Select (CS#) is driven High, the self-timed Chip Erase cycle (whose

duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status Register may be

read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time

before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The

Chip Erase (CE) instruction is ignored if one, or more, sectors are protected.

Figure 14. Chip Erase Instruction Sequence Diagram

Deep Power-down (DP) (B9h)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con-

sumption mode (the Deep Power-down mode). It can also be used as an extra software protection

mechanism, while the device is not in active use, since in this mode, the device ignores all Write,

Program and Erase instructions.

Driving Chip Select (CS#) High deselects the device, and puts the device in the Standby mode (if

there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode.

The Deep Power-down mode can only be entered by executing the Deep Power-down (DP)

instruction, to reduce the standby current (from ICC1 to ICC2, as specified in Table 8.).

Once the device has entered the Deep Power-down mode, all instructions are ignored except the

Release from Deep Power-down and Read Device ID (RDI) instruction. This releases the device

from this mode. The Release from Deep Power-down and Read Device ID (RDI) instruction also

allows the Device ID of the device to be output on Serial Data Output (DO).

The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up

in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (CS#)

Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven

Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15..Chip Select (CS#) must be driven High after the

eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP)

instruction is not executed. As soon as Chip Select (CS#) is driven High, it requires a delay of tDP

before the supply current is reduced to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is

rejected without having any effects on the cycle that is in progress.