AX99100QI datasheet(56/70 Pages) ASIX

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AX99100

PCIe to Multi I/O Controller

AC Timing Characteristics

4.5

4.5.1

PCIe Reference Clock Timing

The reference clock (CLKP and CLKN) of AX99100 is designed for the PCI Express Card Electromechanical

Specification Revision 2.0. Please reference the section 2.1.3 in this standard for the detail.

4.5.2

2C Timing

Symbol

Parameter

Min

Typ

Max

Units

Fclk

SCL clock frequency

SCL will use 100KHz during the configuration

EEPORM loading and can be changed to support

400KHz operating.

100,

400

KHz

Thigh

High period of the SCL clock

SCL_HP+5

Tsys_clk

Tlow

Low period of the SCL clock

SCL_LP+2

Tsys_clk

Thd_sta

Hold time of (repeated) START condition. After

this period, the first clock pulse is generated

SHSC+1

Tsys_clk

Tsu_sta

Setup time for a repeated START condition

SHSC+1

Tsys_clk

Tsu_dat

Data Setup time

(SCL_LP/2)+1

Tsys_clk

Thd_dat

Data hold time

(SCL_LP/2)+1

Tsys_clk

Tsu_sto

Setup time for STOP condition

SCL_HP+5

Tsys_clk

Tbuf

Bus free time between a STOP and START

condition

(SCL_HP/2)+BFT+2

Tsys_clk

Note 1: Tsys_clk = 16ns for 62.5 MHz operating system clock.

Note 2: Fclk = 1/Tclk, where Tclk = ((SCL_HP + SCL_LP) * Tsys_clk). The SCL_HP and SCL_LP are I

2C SCL

Period Register.

Table 4-1: I

2C Master Controller Timing Table

Tsu_sto

Thd_sta

Tsu_sta

Thd_dat

Tlow

Thigh

Tlow

Tsu_dat

Thigh

Thd_sta

Tbuf

SDA

SCL

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