EVAL-ADN2805EBZ datasheet(14/16 Pages) AD

14 / 16 page

ADN2805

Rev. 0 | Page 14 of 16

APPLICATIONS INFORMATION

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. To

reduce series inductance, solder the VEE pins directly to the

ground plane. If the ground plane is an internal plane and

connections to the ground plane are made through vias, multiple

vias can be used in parallel to reduce the series inductance,

especially on Pin 23, which is the ground return for the output

buffers. Connect the exposed pad to the ground plane using

plugged vias to prevent solder from leaking through the vias

during reflow.

Use of a 22 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 μF and 1 nF ceramic chip capacitors,

place them between the IC power supply VCC and VEE, as

close as possible to the ADN2805 VCC pins.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series

inductance, especially on Pin 24, which supplies power to the

high speed CLKOUTP/CLKOUTN and DATAOUTP/

DATAOUTN output buffers. Refer to Figure 14 for the

recommended connections.

By using adjacent power supply and ground planes, excellent

high frequency decoupling can be realized by using close

spacing between the planes. This capacitance is given by

( )

A/d

PLANE =

where:

is the dielectric constant of the PCB material.

A is the area of the overlap of power and ground planes (cm2).

d is the separation between planes (mm).

For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.

50Ω TRANSMISSION LINES

DATAOUTP

DATAOUTN

CLKOUTP

CLKOUTN

0.1µF

22µF

1nF

0.1µF

0.47µF ±20%

>300MΩ INSULATION RESISTANCE

1nF

0.1µF

1nF

VCC

50Ω

OPTICAL

TRANSCEIVER

MODULE

VCC

µC

I2C CONTROLLER

VCC

TEST1

VCC

VREF

NIN

VEE

VCC

VEE

SDA

SCK

SADDR5

VCC

VEE

EXPOSED PAD

TIED OFF TO

VEE PLANE

WITH VIAS

Figure 14. Typical Applications Circuit

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