ADN2805

Rev. 0 | Page 10 of 16

THEORY OF OPERATION

The ADN2805 is a delay- and phase-locked loop circuit for

clock recovery and data retiming from an NRZ encoded data

stream. The phase of the input data signal is tracked by two

separate feedback loops that share a common control voltage. A

high speed delay-locked loop path uses a voltage controlled

phase shifter to track the high frequency components of input

jitter. A separate phase control loop, comprised of the VCO,

tracks the low frequency components of input jitter. The initial

frequency of the VCO is set by yet a third loop, which compares

the VCO frequency with the input data frequency and sets the

coarse tuning voltage. The jitter tracking phase-locked loop

(PLL) controls the VCO by the fine-tuning control.

The delay and phase loops together track the phase of the input

data signal. For example, when the clock lags input data, the

phase detector drives the VCO to a higher frequency and

increases the delay through the phase shifter; both of these

actions serve to reduce the phase error between the clock and

data. The faster clock picks up phase, while simultaneously, the

delayed data loses phase. Because the loop filter is an integrator,

the static phase error is driven to zero.

Another view of the circuit is that the phase shifter implements

the zero required for frequency compensation of a second-order

phase-locked loop, and this zero is placed in the feedback path

and, thus, does not appear in the closed-loop transfer function.

Jitter peaking in a conventional second-order phase-locked loop

is caused by the presence of this zero in the closed-loop transfer

function. Because this circuit has no zero in the closed-loop

transfer, jitter peaking is minimized.

The delay and phase loops together simultaneously provide

wideband jitter accommodation and narrow-band jitter

filtering. The linearized block diagram in Figure 11 shows that

the jitter transfer function, Z(s)/X(s), is second-order low-pass,

providing excellent filtering. Note that the jitter transfer has no

zero, unlike an ordinary second-order phase-locked loop. This

means that the main PLL has virtually zero jitter peaking (see

Figure 12). This makes this circuit ideal for signal regenerator

applications where jitter peaking in a cascade of regenerators

can contribute to hazardous jitter accumulation.

The error transfer, e(s)/X(s), has the same high-pass form as an

ordinary phase-locked loop. This transfer function is free to be

optimized to give excellent wideband jitter accommodation

because the jitter transfer function, Z(s)/X(s), provides the

narrow-band jitter filtering.

X(s)

Z(s)

RECOVERED

CLOCK

e(s)

INPUT

DATA

d/sc

psh

o/s

1/n

d = PHASE DETECTOR GAIN

o = VCO GAIN

c = LOOP INTEGRATOR

psh = PHASE SHIFTER GAIN

n = DIVIDE RATIO

=

1

cn

do

+

n psh

o

s+ 1

Z(s)

X(s)

JITTER TRANSFER FUNCTION

=

d psh

c

s

++

do

cn

e(s)

X(s)

TRACKING ERROR TRANSFER FUNCTION

Figure 11. ADN2805 PLL/DLL Architecture

ADN2805

Z(s)

X(s)

FREQUENCY (kHz)

JITTER PEAKING

IN ORDINARY PLL

o

n psh

d psh

c

Figure 12. ADN2805 Jitter Response vs. Conventional PLL

The delay and phase loops contribute to overall jitter accom-

modation. At low frequencies of input jitter on the data signal,

the integrator in the loop filter provides high gain to track large

jitter amplitudes with small phase error. In this case, the VCO is

frequency modulated and jitter is tracked as in an ordinary

phase-locked loop. The amount of low frequency jitter that can

be tracked is a function of the VCO tuning range. A wider

tuning range gives larger accommodation of low frequency

jitter. The internal loop control voltage remains small for small

phase errors; therefore, the phase shifter remains close to the

center of its range and thus contributes little to the low

frequency jitter accommodation.

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track input jitter. In this case, the

VCO control voltage becomes large and saturates, and the VCO

frequency dwells at either one extreme of its tuning range or at

the other. The size of the VCO tuning range, therefore, has only

a small effect on the jitter accommodation. As such, the delay-

locked loop control voltage is larger, and, consequently, the

phase shifter takes on the burden of tracking the input jitter.

The phase shifter range, in UI, can be seen as a broad plateau on

the jitter tolerance curve. The phase shifter has a minimum

range of 2 UI at all data rates.