ADIS16354SLASHPCBZ datasheet(4/28 Pages) AD

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ADIS16354

Rev. 0 | Page 4 of 28

Parameter

Conditions

Min

Typ

Max

Unit

ADC INPUT

Resolution

Bits

Integral Nonlinearity

±2

LSB

Differential Nonlinearity

±1

LSB

Offset Error

±4

LSB

Gain Error

±2

LSB

Input Range

2.5

Input Capacitance

During acquisition

DAC OUTPUT

5 kΩ/100 pF to GND

Resolution

Bits

Relative Accuracy

For Code 101 to Code 4095

±4

LSB

Differential Nonlinearity

±1

LSB

Offset Error

±5

Gain Error

±0.5

Output Range

2.5

Output Impedance

Output Settling Time

μs

LOGIC INPUTS1

Input High Voltage, VINH

2.0

Input Low Voltage, VINL

0.8

For −CS signal when used to wake up from sleep

mode

0.55

Logic 1 Input Current, IINH

VIH = 3.3 V

±0.2

±10

μA

Logic 0 Input Current, IINL

VIL = 0 V

All Except RST

−40

−60

μA

RST

−1

Input Capacitance, CIN

DIGITAL OUTPUTS1

Output High Voltage, VOH

ISOURCE = 1.6 mA

2.4

Output Low Voltage, VOL

ISINK = 1.6 mA

0.4

SLEEP TIMER

Timeout Period2

0.5

128

Sec

FLASH MEMORY

Endurance3

10,000

Cycles

Data Retention4

TJ = 85°C

Years

CONVERSION RATE

Maximum Sample Rate

SMPL_PRD = 0x01

819.2

SPS

Minimum Sample Rate

SMPL_PRD = 0xFF

0.413

SPS

START-UP TIME5

Initial Power-Up

150

Sleep Mode Recovery

POWER SUPPLY

Operating Voltage Range, VCC

4.75

5.0

5.25

Power Supply Current

Normal mode at 25°C

Fast mode at 25°C

Sleep mode at 25°C

500

μA

1 The digital I/O signals are driven by an internal 3.3 V supply and the inputs are 5 V tolerant.

2 Guaranteed by design.

3 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

4 Retention lifetime equivalent at junction temperature (TJ) 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature.

5 This is defined as the time from wake-up to the first conversion. This time does not include sensor settling time, which is dependent on the filter settings.

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