AD9785-EBZ datasheet(35/64 Pages) AD

35 / 64 page

AD9785/AD9787/AD9788

Rev. 0 | Page 35 of 64

Setting the Frequency of DATACLK

INPUT DATA REFERENCED TO REFCLK

The DATACLK signal is derived from the internal DAC sample

clock, DACCLK. The frequency of DATACLK output depends

on several programmable settings. The relationship between the

frequency of DACCLK and DATACLK is

In some systems, it may be more convenient to use the REFCLK

input instead of the DATACLK output as the input data timing

reference. If the frequency of DACCLK is equal to the frequency

of the data input (PLL is bypassed and no interpolation is used),

the timing parameter “Data with respect to REFCLK” shown in

Table 25 applies directly without further considerations. If the

frequency of DACCLK is greater than the frequency of the data

input, a divider is used to generate the internal data sampling clock

(DCLK_SMP). This divider creates a phase ambiguity between

REFCLK and DCLK_SMP, which, in turn, causes a sampling

time uncertainty. To establish fixed setup and hold times for the

data interface, this phase ambiguity must be eliminated.

DACCLK

DATACLK

where the variables have the values shown in Table 26.

Table 26. DACCLK to DATACLK Divisor Values

Address

Variable

Value

Bits

Interpolation factor

0x01

[7:6]

To eliminate the phase ambiguity, the SYNC_I input pins

(Pin 13 and Pin 14) must be used to synchronize the data to

a specific DCLK_SMP phase. The specific steps for accom-

plishing this are detailed in the

0x01

[4]

0.5 (if single port is enabled)

1 (if dual port is selected)

Device Synchronization section.

The timing relationships between SYNC_I, DACCLK, REFCLK,

and the input data are shown in Figure 49 through Figure 51.

DACCLK

REFCLK

SYNC_I

tS_SYNC

tH_SYNC

INPUT

DATA

tSREFCLK

tHREFCLK

Figure 49. REFCLK 2×

DACCLK

REFCLK

INPUT

DATA

tSREFCLK

tHREFCLK

tS_SYNC

tH_SYNC

SYNC_I

Figure 50. REFCLK 4×

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