LLCC68 datasheet(55/111 Pages) SEMTECH

55 / 111 page

LLCC68

Data Sheet

Rev. 1.1

DS.LLCC68.W.APP

Dec 2024

55 of 111

Semtech

LLCC68

www.semtech.com

9. Operational Modes

The LLCC68 features six operating modes. The analog front-end and digital blocks that are enabled in each operating mode are explained in

the following table.

9.1 Startup

At power-up or after a reset, the chip goes into STARTUP state, the control of the chip being done by the sleep state machine operating at

the battery voltage. The BUSY pin is set to high indicating that the chip is busy and cannot accept a command. When the digital voltage and

RC clock become available, the chip can boot up and the CPU takes control. At this stage the BUSY line goes down and the device is ready

to accept commands.

9.2 Calibration

The calibration procedure is automatically called in case of POR or via the calibration command. Parameters can be added to the calibrate

command to identify which section of calibration should be repeated. The following blocks can be calibrated:

• RC64k using the 32MHz crystal oscillator as reference

• RC13M using the 32MHz crystal oscillator as reference

• PLL to select the proper VCO frequency and division ratio for any RF frequency

• RX ADC

• Image (RX mode with defined tone)

Once the calibration is finished, the chip enters STDBY_RC mode.

Table 9-1: LLCC68 Operating Modes

Mode

Enabled Blocks

SLEEP

Optional registers, backup regulator, RC64k oscillator, data RAM

STDBY_RC

Top regulator (LDO), RC13M oscillator

STDBY_XOSC

Top regulator (DC-DC or LDO), XOSC

All of the above + Frequency synthesizer at Tx frequency

Frequency synthesizer and transmitter, Modem

Frequency synthesizer and receiver, Modem

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