4 Pin Configuration and Functions

1

VCCA 

6

VCCB 

2

GND

5

OE

3

A

4

B

Not to scale

Figure 4-1. DBV Package, 6-Pin SOT-23

(Top View)

1

VCCA 

6

VCCB 

2

GND

5

OE

3

A

4

B

Not to scale

Figure 4-2. DCK Package, 6-Pin SC70

(Top View)

1

VCCA 

2

GND

3

A

4

B

5

OE

6

VCCB 

Not to scale

Figure 4-3. DRL Package, 6-Pin SOT

(Top View)

1

2

C

B

A

Not to scale

A

B

GND

OE

V

CCA

V

CCB

Figure 4-4. YZP Package, 6-Ball DSBGA

(Bottom View)

1

V CCA 

2

GND

3

A

4

B

5

OE

6

V CCB 

Not to scale

Figure 4-5. DRY Package, 6-Pin USON

(Top View)

A.

See mechanical drawings for dimensions.

B.

Pullup resistors are not required on both sides for Logic I/O.

C.

If pullup or pulldown resistors are needed, the resistor value must be over 50kΩ.

D.

50kΩ is a safe recommended value, if the customer can accept higher VOL or lower VOH, smaller pullup or pulldown resistor is allowed,

the draft estimation is VOL = VCCOUT × 4.5k / (4.5k + RPU) and VOH = VCCOUT × RDW / (4.5k + RDW).

E.

If pull up resistors are needed, please refer to the TXS0101 or contact TI.

F.

For detailed information, please refer to application note, A Guide to Voltage Translation With TXB-Type Translators.

www.ti.com

TXB0101

SCES639F – JANUARY 2007 – REVISED SEPTEMBER 2025

Copyright © 2025 Texas Instruments Incorporated

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